Debut of NEC's 3D Graphics Accelerator Technology a Success at SIGGRAPH 2001 Business Wire, August 29, 2001
Business/Technology Editors
BOXBOROUGH, Mass.--(BUSINESS WIRE)--Aug. 29, 2001
Fifth Generation of the NEC TE Graphics Accelerator Series is the
Fastest Ever Produced by the Company
The fastest graphics accelerator technology ever made by NEC was the showcase of the company's technology demonstration at SIGGRAPH 2001 last week in Los Angeles. The technology preview demonstrations, which showed NEC's line of graphics accelerator boards working on high-end, 32-bit systems using CAD, digital content creation, and broadcast postproduction applications, were a precursor to anticipated shipment of NEC's TE 5 graphics accelerator line in the fourth quarter of 2001.
"This was a look into the future of high-end graphics design technology," said Les Silvern, Business Development Manager for Workstation Graphics. "The demonstrations definitely made people think about their creative design possibilities in 2002."
A highlight among the technology demonstrations was NEC's TE 5 HD (High Definition) board, which, when available, will be aimed at the post-production market in preparation for HDTV broadcast. The TE 5 HD and a companion board demonstrated the functionality necessary to synchronize and edit various data streams and create a single output set. The task was performed with one workstation rather than a variety of independent hardware units.
Graphics Accelerator Technology Summary
The NEC TE graphics accelerator series utilizes a unique architecture that implements onboard local memory to store OpenGL display lists and instructions. This technique avoids bus bottlenecks within the workstation and makes display processing independent of other I/O traffic.
Recent Viewperf CDRS-03 tests indicate a projected performance of 65+, which exceeds the closest competitive products. Conservative preliminary estimates of other Viewperf 6.1.2 benchmark scores will be published after I/O driver tuning has been accomplished.
NEC TE 5 technology highlights:
-- Two custom-designed ASICs with 0.18u technology.
1. GRAPE LSI geometry engine -
a highly-tuned 33M vertex/s geometry engine with local memory for accelerating vertex data access. Vertex Pipelines负责前期的建模渲染，处理编程的程序，NV43只是具备3个VS单元，数量不足，在渲染高分辨率的时候直接后果就是前期处理能力不足，导致数据量不足下一级的Pixel Pipelines引擎填充。
2. PEAR LSI rendering engine -
4组像素管线pixel pipelines
and a wide DDR SDRAM interface for unified video memory.
-- Up to 512MB local memory.
-- Up to 256 MB unified video memory for texture and frame buffer.
-- Full-scene anti-aliasing.
显存容量是关乎到像素着色器（Pixel Pipelines）的处理，主要在纹理贴图中起重要的作用，但是显存容量并不是越多越好的 The TE 5B and HD are expected to be announced in the US and Europe this fall and to appear in workstations from industry-leading vendors early next year.
Further details about NEC's TE 5 technology are available on the Web at: www.neccomp.com/graphics.
发表于 2008-12-20 20:39
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